Circuit boards for the IoT world (Internet of Things) are often driven by the need for low power dissipation, low cost (which drives very low layer count), moderate to high-density and mixed-signal applications. This combination of needs can make board design an extreme challenge. Creating a 1-, 2- or 4-layer board, with excellent signal integrity and low noise/interference and no EMI issues can, by itself, be a very serious challenge. This 3.5-hour course will discuss how to understand when it is necessary to control impedance of lines, how to do it cost-effectively, proper setup of routed lines to keep circuit energy from spreading (preventing interference), even on a one layer board, design of antenna into the PCB, circuit grounding in low layer count boards, power distribution without the benefit of power planes, ground bounce, cross talk with low layer count and design to optimize manufacturability of low layer count PCBs.
Signal degradation on PCB transmission lines manifests in many forms: undershoot, overshoot, ringing, pulse shape distortion, switching noise, attenuation, ground bounce, skew, etc. All these can be attributed to one or more of these sources: signal reflections caused by characteristic impedance discontinuities; signal distortion due to conductor and dielectric losses resulting from PCB materials’ properties as signals travel over the transmission lines; crosstalk from signals on nearby PCB conductors; noise in power distribution network; electromagnetic interference (EMI). Impedance discontinuities manifest from many sources, to name a few: unmatched loads and terminations, non-uniformity in the lines, vias, stubs, component and test pads, gaps in reference planes and poorly designed return paths, stray capacitances and inductances, and branching of signal paths, and all these cause signal reflections. Frequency dependence of the copper and dielectric losses cause unequal attenuation of various frequency contents in the signals, causing signal rise time degradation, and variations in dielectric constant with frequency cause different frequency signal components traveling at different speeds.
Crosstalk from nearby conductors occurs due to inductive and capacitive coupling, causing several issues: near- and far-end crosstalk, switching noise, ground bounce, etc. PDN noise and unwanted electromagnetic energy will superimpose on signals causing signal integrity issues. After identifying the root cause, one can find solutions to the signal integrity problem.
Differential pairs have been used in PC boards for years to carry high-speed serial and high-speed parallel data, in a variety of bus formats. Many board designers and engineers believe the rules for differential pairs are the same in a PCB as they are in cable or twisted pairs of wires. This is usually not the case!
This course will cover the advantages of differential pairs vs. single-ended lines, which differential pair format gives the best impedance control, what is the right spacing between the lines of a pair, crosstalk between differential pairs, what is important in differential pair routing, how much timing skew is really acceptable, the impact of material type and the impact of vias on signal integrity and EMI.
This comprehensive seminar of how to design a PCB stackup to optimize performance while attaining the lowest cost possible. With the advent of very high-speed signaling along with multiple very high-current power supply rails, it is necessary to understand how materials behave and how PCBs are fabricated in order to arrive at a PCB stackup that results in a “right the first time” design. The seminar draws from the speaker’s long experience designing PCB stackup for products ranging from video games to supercomputers. It draws on the results of dozens of test PCBs used to characterize materials from a loss and high-speed skew perspective.
This half-day course is an overview (past, present, and future) of the interactions of processes, people and technologies involved in the complete lifecycle of a PCB design. This course is designed to provide a solid foundation for those who are just starting out (zero to two years of experience) as a PCB designer and help the individual formulate a roadmap to build their knowledge base for both personal and career advancement as contributors to this industry. All attendees will receive an MS Excel checklist of the traditional questions that PCB designers should ask throughout the PCB design process.
This session is intended for board designers to understand the things RF engineers request during PCB layout. Experienced RF engineers will likely not learn anything new from this course, as the material is mainly geared to board designers.
Due to sensitivity in analog circuits, the keys to full functionality (whether you are designing very high-frequency analog PC boards, mixing RF with digital or mixing low-frequency analog with digital) are signal integrity and noise control in the design of the printed circuit board. This course will cover differences between analog and digital, circuit changes over time, lumped vs. distributed length lines, reflections/return loss/VSWR, low- and high-frequency current, transmission line behavior, impedance control, microstrip vs. stripline, coplanar waveguide w/ ground, circuit termination, 1/4 wavelength couplers and filters designed into board copper, layout techniques and strategies, critical routing and circuit isolation, ground plane splitting (when to and when not to), mismatched loads and other discontinuities, signal splitters, tuning transmission lines, power bus decoupling for RF vs. digital circuits and board stack-ups for mixed RF and digital circuits.
What is a wire? At high speeds, it behaves very differently from what we were taught in college. This presentation on high-speed basics makes the subject intuitive in a way that’s easily understood. Learn about how frequency enters the picture, high-speed signal propagation, impedance, noise, and reflections with easy-to-understand animations and analogies to understand this subject on a deeper level.
Supply voltages decrease with every new silicon generation, contributing as well to the goal of reducing power consumption of our electronics. Coupled with the resulting shrinking noise margins for these ICs, this defines increasing demands for the quality and stability of power distribution schemes of PCBs. Hence, tighter requirements and constraints from silicon vendors are defined for power distribution networks (PDN), which PCB designers follow, in conjunction with tighter decoupling schemes. Board real estate limitations, application-dependent restrictions (e.g., discrete package size allowance in automotive) and cost demands further complicate the game. To address these technical challenges, engineers need to evolve from working within a disconnected design process to new or advanced design methodology with power-integrity and the demands of the PDN in mind. Using such a methodology and smart mechanisms to optimize the decoupling scheme can help ensure a design will meet the electrical specifications for power. In this two-hour workshop, the requirements and basics of PCB power distribution systems are explained in detail. The whole problem area, ranging from DC (with aspects like IR-drop, DC voltages and current distributions) to AC with its phenomena (e.g., target impedance, decoupling, inductance), is covered. Topics like plate capacitance, loop inductance and cavity resonance are explained in detail but without deep math. Side effects to the signal integrity and EMC behavior of board structures are discussed using illustrated practical examples. The role of capacitors, their parasitic behavior (ESL, ESR, connection inductance) and the technical decoupling evolution in recent years are a major part of the workshop. Guidelines for a first order covering and resolving power integrity issues are provided, regardless of the PCB design and ECAD process. Simulation capabilities addressing power integrity during PCB design will be explained and demonstrated by slides in a generic vendor-neutral manner as a problem-solving approach. Silicon vendor support documents (e.g. constraint and spreadsheet tools) to address power integrity are introduced and briefly discussed. Examples from various industries (e.g., automotive, industry automation, IoT) will complement the session with practical application experience.
This presentation will present a simple EM physics and geometry-based approach to designing power distribution networks on PCBs. From input power connection to the IC die, the simple rules discussed can be used to reduce power supply noise and improve EMC. New research is presented on the impact of discrete components on radiated and conducted emissions, with an emphasis on cost analysis. This course will, after an introduction to EM field behavior, describe several effective methods for designing the spaces used to deliver power on a PCB. These methods are driven by considerations for how fast the switches are changing states and the geometry of the spaces and placement of components to properly delivery energy to prevent EMC and signal integrity issues.
When time-varying (AC) signals travel in the transmission lines of a board, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years ICs with very fast rise time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding will help contain and control fields, making noise and EMI issues virtually nonexistent. This 3.5-hour course will focus on the issues PCB designers and engineers need to know to prevent noise, EMI and grounding problems in today’s circuits. We will discuss what is meant by “grounding,” where energy travels in the board, location of high- and low-frequency currents, keys to controlling common mode EMI, cables and other unintended radiators, effects of IC style and packaging on overall grounding, impact of connector pin-out, best locations for IO connectors, divided planes and plane islands in the PCB, routing to control noise, best board stack-ups and filtering of single-ended and differential I/O lines.