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BTS035 Inductance Analysis of Chip Scale Packages

BTS035 Inductance Analysis of Chip Scale Packages

By Eric Bogatin, David Light and Bill Beale, published in 1999 Chip Scale International Conference, San Jose, CA, Sept. 15, 1999
One of the advantages of chip scale packages is their short total path lengths and, hence, low electrical parasitics. For signal paths, the inductive discontinuity of the leads may not be a serious limitation. However, for power and ground distribution, the loop inductance can pose the most important limitation to the highest possible operating clock frequency. In this paper, we develop a simple model to relate the maximum operating clock frequency of a CSP, based on the power dissipation of the chip, the typical lead equivalent inductance, and the number of pairs of leads used for power and ground. Given the significance of the inductance, we illustrate how the equivalent inductance of the leads can be minimized. Finally, for detailed analysis, we show how a field solver can be used to extract the complete inductance description of a CSP.

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